Circuit designers are often required to deal with design constraints such as: speed, power, cost, and size. Generally speaking, optimizing one design parameter often requires a sacrifice in performance of one or more of the other design parameters. Where the shortest switching time is desired, for example, a higher quiescent power requirement may be necessitated. Alternately, a higher density of gates per square inch of die may increase die area usage efficiency, but may also reduce gate geometries, thus limiting current conduction capability. Other design considerations, such as cost effectiveness, are also high on the priority list for circuit designers.
The technology used to fabricate integrated circuits can present a unique set of cost constraints to the circuit designer as compared to a discrete realization of the same circuit. For example, one cost determining factor with integrated circuits is the number of Input/Output (I/O) pins that may be required. Some integrated circuit designs, for example, require capacitive loading to create a power supply bypass for increased noise immunity. Bypass capacitors used in some discrete circuit designs, however, are prohibitive in an integrated circuit implementation due to the feasibility of construction of the larger-sized capacitors on the die. If capacitors are required, therefore, they must be external to the integrated circuit which adds pin count and drives the cost of the integrated circuit design upward. Capacitor-free integrated circuit designs, therefore, are generally highly desirable.
Another design constraint for integrated circuit design is die area. Generally speaking, the least-expensive component that can be fabricated on the integrated circuit is the component that requires the least amount of die area, usually a transistor. Thus, a circuit realization that contains a minimum total number of passive components, while using a greater number of active components may be optimum.
One area of integrated circuit design that has been under considerable design scrutiny is the emitter-coupled, or alternatively, the source-coupled pair configuration of the differential amplifier. One example of the usefulness of this circuit stems from the fact that cascades of the emitter-coupled, or source-coupled, pairs may be implemented without the need for capacitive coupling. Also, the differential characteristics of this circuit type, e.g., common mode rejection, is also a highly desirable characteristic.
In some conventional differential amplifier designs, active components may be used as the load elements to increase the gain of the devices. Active load elements, however, tend to add noise to the output, either in the form of shot noise, as is the case with bipolar designs, or in the form of thermal or flicker noise, as is the case with all active load designs.
In other differential amplifier designs, passive loading may be used to reduce output noise, but may suffer from power supply noise rejection. The resistive load, for example, is generally connected between the collector, or drain, of each transistor of the output stage differential pair and the top rail power supply. In such a configuration, any power supply noise or ripple is almost directly translated to the output via the resistive load. Such Amplitude Modulated (AM) noise translates to Phase Modulated (PM) noise and produces phase jitter.
As technology associated with integrated circuit design progresses, alternate forms of loading and common mode voltage ripple cancellation are developed to reduce phase jitter associated with power supply noise. An apparatus and method that advances the art of canceling common mode voltage variation, and other related problems, continues to be desirable.